1. Field of the Invention
The present invention is directed to memory arrays used in the design of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to the design of self-timed memory arrays.
2. Description of Related Art
Different types and sizes of memory arrays typically used in integrated circuit designs operate at different speeds. One method of accommodating read control circuitry to a specific memory speed is to insert a selectable fixed timing delay after a clock signal to trigger the sense amplifiers of a memory array after a sufficient interval has passed to ensure a correct reading of a data cell. A disadvantage of using a fixed timing delay is that the amount of delay required varies within a range determined by processing characteristics and other factors, complicating the design of memory array read/write circuits. Simply using a large delay would sacrifice the performance speed of the memory array, resulting in a loss of competitiveness with other memory array designs. In a self-timed memory array, the timing delay of the sense amplifier trigger signal is matched to the timing delay of the data bit lines of the memory array by deriving the timing of the sense amplifier trigger signal from a selectable number of self-timed pull-down core cells that have a structure identical to that of the data cells in the memory array. The self-timed pull-down core cells generate a self-timed bit line signal that controls the amount of delay before the sense amplifier is triggered, compensating automatically for process variations and memory size. Because the timing of the sense amplifier trigger signal is determined by the same type of core cells used in the memory array, the memory array is called a self-timed memory array.